/** @file
Parameter configuration.

Copyright (C) 2022 - 2023, Phytium Technology Co., Ltd. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

**/
#include <Library/ParameterTable.h>

/**
  Get partmeter table base address.

  @param[in]  Id  Parameter tabe identifier
                  PM_PLL_V1      PLL V1 for Pd2008/Ps2364.
                  PM_PLL_V2      PLL V2 for Pe2204.
                  PM_PCIE_V1     PCIE V1 for Pd2008.
                  PM_PCIE_V2     PCIE V2 for Pe2204.
                  PM_COMMON_V1   Common V1 for Pd2008/Pe2204.
                  PM_DDR_V1      DDR V1 for Pd2008.
                  PM_DDR_V2      DDR V2 for Pe2204.
                  PM_DDR_V3      DDR V3 for Ps2364.
                  PM_BOARD       Board.
                  PM_BOARD_V2    Board for Ps2364
                  PM_COMMON_V2   Common V2 for Ps2364.
                  PM_C2C         C2C for Ps2364.
                  Other          Invalid ID.


  @retval  Head    Pointer to parameter base address
  @retval  NULL    Magic mismatch.
**/
VOID *
GetParameterBase (
  IN UINT32 Id
  )
{
  PARAMETER_HEADER *Head;
  UINT32           Offset;
  UINT32           Magic;

  switch (Id) {
  case PM_PLL_V1:
    Offset = PM_PLL_OFFSET;
    Magic = PARAMETER_PLL_MAGIC_V1;
    break;
  case PM_PLL_V2:
    Offset = PM_PLL_OFFSET;
    Magic = PARAMETER_PLL_MAGIC_V2;
    break;
  case PM_PCIE_V1:
    Offset = PM_PCIE_OFFSET;
    Magic = PARAMETER_PCIE_MAGIC_V1;
    break;
  case PM_PCIE_V2:
    Offset = PM_PCIE_OFFSET;
    Magic = PARAMETER_PCIE_MAGIC_V2;
    break;
  case PM_PCIE_V3:
    Offset = PM_PCIE_OFFSET;
    Magic = PARAMETER_PCIE_MAGIC_V3;
    break;
  case PM_COMMON_V1:
    Offset = PM_COMMON_OFFSET;
    Magic = PARAMETER_COMMON_MAGIC_V1;
    break;
  case PM_DDR_V1:
    Offset = PM_DDR_OFFSET;
    Magic = PARAMETER_DDR_MAGIC_V1;
    break;
  case PM_DDR_V2:
    Offset = PM_DDR_OFFSET;
    Magic = PARAMETER_DDR_MAGIC_V2;
    break;
  case PM_DDR_V3:
    Offset = PM_DDR_OFFSET;
    Magic = PARAMETER_DDR_MAGIC_V3;
    break;
  case PM_BOARD:
    Offset = PM_BOARD_OFFSET;
    Magic = PARAMETER_BOARD_MAGIC;
    break;
  case PM_BOARD_V2:
    Offset = PM_BOARD_OFFSET;
    Magic = PARAMETER_BOARD_MAGIC_V2;
    break;
  case PM_SECURE:
    Offset = PM_SECURE_OFFSET;
    Magic = PARAMETER_BOARD_MAGIC;
    break;
  case PM_COMMON_V2:
    Offset = PM_COMMON_OFFSET;
    Magic = PARAMETER_COMMON_MAGIC_V2;
    break;
  case PM_C2C:
    Offset = PM_C2C_OFFSET;
    Magic = PARAMETER_C2C_MAGIC;
    break;
  default:
    DEBUG((DEBUG_ERROR, "Invalid Id : %d\n", Id));
    while(1);
  }

  Head = (PARAMETER_HEADER *) (UINT64) (O_PARAMETER_BASE + Offset);
  if (Magic != Head->Magic) {
    return NULL;
  } else {
    return (VOID *) (Head);
  }
}

/**
  Get Parameter information.

  @param[in]      Id        Parameter tabe identifier.
                            PM_PLL_V1      PLL V1 for Pd2008/Ps2364.
                            PM_PLL_V2      PLL V2 for Pe2204.
                            PM_PCIE_V1     PCIE V1 for Pd2008.
                            PM_PCIE_V2     PCIE V2 for Pe2204.
                            PM_COMMON_V1   Common V1 for Pd2008/Pe2204.
                            PM_DDR_V1      DDR V1 for Pd2008.
                            PM_DDR_V2      DDR V2 for Pe2204.
                            PM_DDR_V3      DDR V3 for Ps2364.
                            PM_BOARD       Board.
                            PM_BOARD_V2    Board for Ps2364.
                            PM_COMMON_V2   Common V2 for Ps2364.
                            PM_C2C         C2C for Ps2364.
                            Other          Invalid ID.
  @param[in,out]  Data      Pointer to paramter information.
  @param[in]      DataSize  Data size to get.

  @retval  EFI_SUCCESS    Get information suceess
  @retval  EFI_NOT_FOUND  Get fail
  @retval  EFI_BUFFER_TOO_SMALL   Buffer size is to small.
  @retval  EFI_INVALID_PARAMETER  Data is NULL, DataSize is 0.

**/
EFI_STATUS
GetParameterInfo (
  IN     UINT32 Id,
  IN OUT UINT8 *Data,
  IN     UINT32 DataSize
  )
{
  PARAMETER_HEADER *Head;

  if((Data == NULL) || (DataSize == 0)) {
    return EFI_INVALID_PARAMETER;
  }

  Head = (PARAMETER_HEADER *) GetParameterBase (Id);
  DEBUG ((DEBUG_INFO, "Id : %x, Head : %x\n", Id, Head));
  if(Head == NULL) {
    return EFI_NOT_FOUND;
  }

  if(DataSize < Head->Size) {
    DEBUG ((DEBUG_ERROR, "DataSize is too small\n", DataSize));
    return EFI_BUFFER_TOO_SMALL;
  }

  CopyMem (Data, Head, Head->Size);

  return EFI_SUCCESS;
}

/**
  Get Peie V3 information.

  @param[in]      Id        Parameter tabe identifier.
  @param[in]      DieNum    Number of die to get.
  @param[in,out]  Data      Pointer to paramter information.
  @param[in]      DataSize  Data size to get.

  @retval  EFI_SUCCESS            Get information suceess.
  @retval  EFI_INVALID_PARAMETER  Data is NULL, DataSize is 0, or ID is not
                                  PARAMETER_PCIE_MAGIC_V3
  @retval  EFI_NOT_FOUND          Get fail.
  @retval  EFI_BUFFER_TOO_SMALL   Buffer size is to small.
**/
EFI_STATUS
GetParameterPcieV3 (
  IN     UINT32 Id,
  IN     UINT8  DieNum,
  IN OUT UINT8 *Data,
  IN     UINT32 DataSize
  )
{
  PARAMETER_HEADER *Head;

  if((Data == NULL) || (DataSize == 0)) {
    return EFI_INVALID_PARAMETER;
  }

  if (Id != PM_PCIE_V3) {
    return EFI_INVALID_PARAMETER;
  }

  Head = (PARAMETER_HEADER *) GetParameterBase (Id);
  DEBUG ((DEBUG_INFO, "Id : %x, Head : %x\n", Id, Head));
  if(Head == NULL) {
    return EFI_NOT_FOUND;
  }

  if(DataSize < Head->Size) {
    DEBUG ((DEBUG_ERROR, "DataSize is too small\n", DataSize));
    return EFI_BUFFER_TOO_SMALL;
  }

  CopyMem (Data, (VOID *)((UINT64)Head + DieNum * PM_PCIE_OFFSET_DIE_V3), Head->Size);

  return EFI_SUCCESS;
}

/**
  Get Secure Parameter information.

  @param[in]      Id    parameter tabe identifier
  @param[in,out]  Data  pointer to paramter information.
  @param[in]      Size  Size of data to get.

  @retval  EFI_SUCCESS            Get information suceess
  @retval  EFI_INVALID_PARAMETER  Get fail.

**/
EFI_STATUS
GetParameterSecureInfo (
  IN     UINT32 Id,
  IN OUT UINT8  *Data,
  IN     UINT32 Size
  )
{
  UINT64               SecureAddr;

  if (Id != PM_SECURE) {
    return EFI_INVALID_PARAMETER;
  }

  SecureAddr = O_PARAMETER_BASE + PM_SECURE_OFFSET;

  CopyMem (Data, (VOID *)SecureAddr, sizeof(DDR_SECURE_CONFIG));

  return EFI_SUCCESS;
}

/**
  Get die number only for Ps2364.

  @param[out]  Num    Die num.

  @retval      EFI_SUCCESS    Success.
  @retval      Other          Failed.
**/
EFI_STATUS
GetDieNumFromParTable (
  OUT UINT8  *Num
  )
{
  UINT8                    Buffer[0x100];
  PARAMETER_C2C_CONFIG     *C2CConfig;
  EFI_STATUS               Status;

  ZeroMem (Buffer, 0x100);
  Status = EFI_SUCCESS;

  Status = GetParameterInfo (PM_C2C, Buffer, 0x100);
  if (EFI_ERROR (Status)) {
    *Num = 0;
  } else {
    C2CConfig = (PARAMETER_C2C_CONFIG *) Buffer;
    *Num = C2CConfig->Head.DieID;
  }
  DEBUG ((DEBUG_INFO, "Die Num : %d, Status : %r", *Num, Status));

  return Status;
}

/**
  Print parameter header information.

  @param[in]  Buffer    Buffer to print.

**/
VOID
PrintParameterHeader (
  IN  VOID  *Buffer
  )
{
  PARAMETER_HEADER  *Head;

  Head = (PARAMETER_HEADER *) Buffer;

  DEBUG ((DEBUG_INFO, "Pameter Header :\n"));
  DEBUG ((DEBUG_INFO, "Magic : 0x%08x\n", Head->Magic));
  DEBUG ((DEBUG_INFO, "Version : 0x%08x\n", Head->Version));
  DEBUG ((DEBUG_INFO, "Size : 0x%08x\n", Head->Size));
  DEBUG ((DEBUG_INFO,
          "Reserved : %02x-%02x-%02x-%02x\n",
          Head->DieID,
          Head->Reserved[0],
          Head->Reserved[1],
          Head->Reserved[2]
          ));
}

/**
  Print C2C parameter information, only for Ps2364.

  @param[in]  Id      Parameter ID. PM_C2C.
  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintC2CParameter (
  IN  UINT32  Id,
  IN  VOID    *Buffer
  )
{
  PARAMETER_C2C_CONFIG     *C2CPar;
  UINT32                   Index;
  UINT32                   Index1;

  DEBUG ((DEBUG_INFO, "C2C Parameter :\n"));
  switch (Id) {
  case PM_C2C:
    C2CPar = (PARAMETER_C2C_CONFIG *) Buffer;
    PrintParameterHeader ((VOID *) &C2CPar->Head);
    for (Index = 0; Index < 7; Index++) {
      DEBUG((DEBUG_INFO, "DIE[%d] : \n", Index));
      DEBUG ((DEBUG_INFO,
              "C2C Enable : 0x%x\n",
              (C2CPar->C2CEnable.Uint32 >> (Index * 4)) & 0xF
              ));
      DEBUG ((DEBUG_INFO, "Ras Enable : 0x%x\n", C2CPar->C2CConfig[Index].RasConfig.RasEnable.Bits.Enable));
      DEBUG ((DEBUG_INFO, "Ras Value : 0x%x\n", C2CPar->C2CConfig[Index].RasConfig.Value));
      DEBUG ((DEBUG_INFO, "Speed : 0x%x\n", C2CPar->C2CConfig[Index].Speed.Uint32));
      for (Index1 = 0; Index1 < 4; Index1++) {
        DEBUG ((DEBUG_INFO, "Equal Value[%d] : 0x%x\n", Index1, C2CPar->C2CConfig[Index].EqualValue[Index1]));
      }
    }
    break;
  default:
    break;
  }
}

/**
  Print PLL parameter information.

  @param[in]  Id      Parameter ID. PM_PLL_V1 for Pd2008/Ps2364,
                      PM_PLL_V2 for Pe2204.
  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintPllParameter (
  IN  UINT32  Id,
  IN  VOID    *Buffer
  )
{
  PARAMETER_PLL_CONFIG_V1  *PllParV1;
  PARAMETER_PLL_CONFIG_V2  *PllParV2;

  DEBUG ((DEBUG_INFO, "PLL Parameter :\n"));
  switch (Id) {
  case PM_PLL_V1:
    PllParV1 = (PARAMETER_PLL_CONFIG_V1 *) Buffer;
    PrintParameterHeader ((VOID *) &PllParV1->Head);
    DEBUG ((DEBUG_INFO, "Core Frequence : %d\n", PllParV1->CoreFreq));
    DEBUG ((DEBUG_INFO, "Lmu Frequence : %d\n", PllParV1->LmuFreq));
    break;
  case PM_PLL_V2:
    PllParV2 = (PARAMETER_PLL_CONFIG_V2 *) Buffer;
    PrintParameterHeader ((VOID *) &PllParV2->Head);
    DEBUG ((DEBUG_INFO, "Performance Core Frequence : %d\n", PllParV2->PerformanceCoreFreq));
    DEBUG ((DEBUG_INFO, "Efficiency Core Frequence : %d\n", PllParV2->EfficiencyCoreFreq));
    DEBUG ((DEBUG_INFO, "Lmu Frequence : %d\n", PllParV2->LmuFreq));
    break;
  default:
    break;
  }
}

/**
  Print COMMON parameter information.

  @param[in]  Id      Parameter ID.
                      PM_COMMON_V1 for Pd2008/Pe2204.
                      PM_COMMON_V2 for Ps2364
  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintCommonParameter (
  IN  UINT32  Id,
  IN  VOID    *Buffer
  )
{
  PARAMETER_COMMON_CONFIG_V1  *CommonParV1;
  PARAMETER_COMMON_CONFIG_V2  *CommonParV2;
  UINT32                      Index;

  DEBUG ((DEBUG_INFO, "Common Parameter :\n"));
  switch (Id) {
  case PM_COMMON_V1:
    CommonParV1 = (PARAMETER_COMMON_CONFIG_V1 *) Buffer;
    PrintParameterHeader ((VOID *) &CommonParV1->Head);
    DEBUG ((DEBUG_INFO, "Core Map : 0x%llx\n", CommonParV1->CoreBitMap));
    DEBUG ((DEBUG_INFO, "MISC1 Function : 0x%lx\n", CommonParV1->Misc1));
    break;
  case PM_COMMON_V2:
    CommonParV2 = (PARAMETER_COMMON_CONFIG_V2 *) Buffer;
    PrintParameterHeader ((VOID *) &CommonParV2->Head);
    for (Index = 0; Index < 8; Index++) {
      DEBUG ((DEBUG_INFO, "DIE[%d], ", Index));
      DEBUG ((DEBUG_INFO, "Core Map : 0x%llx\n", CommonParV2->CoreBitMap[Index]));
    }
    DEBUG ((DEBUG_INFO, "MISC1 Function : 0x%x\n", CommonParV2->Misc1));
    break;
  default:
    break;
  }
}

/**
  Print PCIE parameter information.

  @param[in]  Id      Parameter ID.
                      PM_PCIE_V1 for Pd2008.
                      PM_PCIE_V2 for Pe2204.
                      PM_PCIE_V3 for Ps2364.
  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintPcieParameter (
  IN  UINT32  Id,
  IN  VOID    *Buffer
  )
{
  PARAMETER_PCIE_CONFIG_V1  *PcieParV1;
  PARAMETER_PCIE_CONFIG_V2  *PcieParV2;
  PARAMETER_PCIE_CONFIG_V3  *PcieParV3;
  UINT32                    Index;

  DEBUG ((DEBUG_INFO, "PCIE Parameter :\n"));
  switch (Id) {
  case PM_PCIE_V1:
    PcieParV1 = (PARAMETER_PCIE_CONFIG_V1 *) Buffer;
    PrintParameterHeader ((VOID *) &PcieParV1->Head);
    DEBUG ((DEBUG_INFO, "PCIE 0 :\n"));
    DEBUG ((DEBUG_INFO, "Split : 0x%x\n", PcieParV1->Function.Bits.Pcie0Split));
    DEBUG ((DEBUG_INFO, "Mode : 0x%x\n", PcieParV1->Function.Bits.Pcie0Mode));
    for (Index = 0; Index < 3; Index++) {
      DEBUG ((DEBUG_INFO,
              "Controller[%d] : Speed-0x%x, Enable-0x%x, EqualValue-0x%x\n",
              Index,
              PcieParV1->Pcie0Config.BaseConfig[Index].Bits.Speed,
              PcieParV1->Pcie0Config.BaseConfig[Index].Bits.Enable,
              PcieParV1->Pcie0Config.EqualValue[Index].Bits.Value
              ));
    }
    DEBUG ((DEBUG_INFO, "PCIE 1 :\n"));
    DEBUG ((DEBUG_INFO, "Split : 0x%x\n", PcieParV1->Function.Bits.Pcie1Split));
    DEBUG ((DEBUG_INFO, "Mode : 0x%x\n", PcieParV1->Function.Bits.Pcie1Mode));
    for (Index = 0; Index < 3; Index++) {
      DEBUG ((DEBUG_INFO,
              "Controller[%d] : Speed-0x%x, Enable-0x%x, EqualValue-0x%x\n",
              Index,
              PcieParV1->Pcie1Config.BaseConfig[Index].Bits.Speed,
              PcieParV1->Pcie1Config.BaseConfig[Index].Bits.Enable,
              PcieParV1->Pcie1Config.EqualValue[Index].Bits.Value
              ));
    }
    break;
  case PM_PCIE_V2:
    PcieParV2 = (PARAMETER_PCIE_CONFIG_V2 *) Buffer;
    PrintParameterHeader ((VOID *) &PcieParV2->Head);
    DEBUG ((DEBUG_INFO, "PCIE 0:"));
    DEBUG ((DEBUG_INFO, "Split : 0x%x\n", PcieParV2->Function.Bits.Pcie0Split));
    for (Index = 0; Index < 2; Index++) {
      DEBUG ((DEBUG_INFO,
              "Controller[%d] : Speed-0x%x, Disable-0x%x, Mode-0x%x, EqualValue-0x%x\n",
              Index,
              PcieParV2->Pcie0Config[Index].Bits.Speed,
              PcieParV2->Pcie0Config[Index].Bits.Close,
              PcieParV2->Pcie0Config[Index].Bits.Mode,
              PcieParV2->Pcie0EqualValue[Index].Bits.Value
              ));
    }
    DEBUG ((DEBUG_INFO, "PCIE 1:"));
    DEBUG ((DEBUG_INFO, "Split : 0x%x\n", PcieParV2->Function.Bits.Pcie1Split));
    for (Index = 0; Index < 4; Index++) {
      DEBUG ((DEBUG_INFO,
              "Controller[%d] : Speed-0x%x, Disable-0x%x, EqualValue-0x%x\n",
              Index,
              PcieParV2->Pcie1Config[Index].Bits.Speed,
              PcieParV2->Pcie1Config[Index].Bits.Close,
              PcieParV2->Pcie1EqualValue[Index].Bits.Value
              ));
    }
    break;
  case PM_PCIE_V3:
    PcieParV3 = (PARAMETER_PCIE_CONFIG_V3 *) Buffer;
    PrintParameterHeader ((VOID *) &PcieParV3->Head);
    DEBUG ((DEBUG_INFO, "DIE [%d] :\n", PcieParV3->Head.DieID));
    DEBUG ((DEBUG_INFO,
            "Split : PCIE0-0x%x, PCIE1-0x%x, PCIE2-0x%x,PCIE3-0x%x\n",
             PcieParV3->Split.Bits.Mode0,
             PcieParV3->Split.Bits.Mode1,
             PcieParV3->Split.Bits.Mode2,
             PcieParV3->Split.Bits.Mode3
            ));
    DEBUG ((DEBUG_INFO,
            "Advanced Function : HotPlug-%x, AER-%x, ARI-%x, ASPM-%x\n",
            PcieParV3->Advanced.Bits.HotPlug,
            PcieParV3->Advanced.Bits.Aer,
            PcieParV3->Advanced.Bits.Ari,
            PcieParV3->Advanced.Bits.Aspm
            ));
    DEBUG ((DEBUG_INFO,
            "RAS : Enable-%x, Value-0x%x\n",
            PcieParV3->RasConfig.RasEnable.Bits.Enable,
            PcieParV3->RasConfig.Value
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 0 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C0Close,
            PcieParV3->Speed.Bits.C0Speed,
            PcieParV3->EqualValue[0],
            PcieParV3->PhysicalSlotNum[0]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 1 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C1Close,
            PcieParV3->Speed.Bits.C1Speed,
            PcieParV3->EqualValue[1],
            PcieParV3->PhysicalSlotNum[1]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 2 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C2Close,
            PcieParV3->Speed.Bits.C2Speed,
            PcieParV3->EqualValue[2],
            PcieParV3->PhysicalSlotNum[2]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 3 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C3Close,
            PcieParV3->Speed.Bits.C3Speed,
            PcieParV3->EqualValue[3],
            PcieParV3->PhysicalSlotNum[3]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 4 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C4Close,
            PcieParV3->Speed.Bits.C4Speed,
            PcieParV3->EqualValue[4],
            PcieParV3->PhysicalSlotNum[4]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 5 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C5Close,
            PcieParV3->Speed.Bits.C5Speed,
            PcieParV3->EqualValue[5],
            PcieParV3->PhysicalSlotNum[5]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 6 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C6Close,
            PcieParV3->Speed.Bits.C6Speed,
            PcieParV3->EqualValue[6],
            PcieParV3->PhysicalSlotNum[6]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 7 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C7Close,
            PcieParV3->Speed.Bits.C7Speed,
            PcieParV3->EqualValue[7],
            PcieParV3->PhysicalSlotNum[7]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 8 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C8Close,
            PcieParV3->Speed.Bits.C8Speed,
            PcieParV3->EqualValue[8],
            PcieParV3->PhysicalSlotNum[8]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 9 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C9Close,
            PcieParV3->Speed.Bits.C9Speed,
            PcieParV3->EqualValue[9],
            PcieParV3->PhysicalSlotNum[9]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 10 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C10Close,
            PcieParV3->Speed.Bits.C10Speed,
            PcieParV3->EqualValue[10],
            PcieParV3->PhysicalSlotNum[10]
            ));
    DEBUG ((DEBUG_INFO,
            "Controller 11 : Disable-%x, Speed-%x, EqualValue-0x%x, Slot-0x%x\n",
            PcieParV3->Enable.Bits.C11Close,
            PcieParV3->Speed.Bits.C11Speed,
            PcieParV3->EqualValue[11],
            PcieParV3->PhysicalSlotNum[11]
            ));
    break;
  default:
    break;
  }
}

/**
  Print DDR parameter information.

  @param[in]  Id      Parameter ID.
                      PM_DDR_V1 for Pd2008.
                      PM_DDR_V2 for Pe2204.
                      PM_DDR_V3 for Ps2364.
  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintDdrParameter (
  IN UINT32  Id,
  IN VOID    *Buffer
  )
{
  PARAMETER_DDR_CONFIG_V1  *DdrParV1;
  PARAMETER_DDR_CONFIG_V2  *DdrParV2;
  PARAMETER_DDR_CONFIG_V3  *DdrParV3;
  UINT32                   Index;

  DEBUG ((DEBUG_INFO, "DDR Parameter :\n"));
  switch (Id) {
  case PM_DDR_V1:
    DdrParV1 = (PARAMETER_DDR_CONFIG_V1 *) Buffer;
    PrintParameterHeader ((VOID *) &DdrParV1->Head);
    DEBUG ((DEBUG_INFO,
            "Channel Enable : Ch0-%x, Ch1-%x\n",
            DdrParV1->ChEnable.Bits.Ch0,
            DdrParV1->ChEnable.Bits.Ch1
            ));
    DEBUG ((DEBUG_INFO, "Mcu Base Config :\n"));
    DEBUG ((DEBUG_INFO, "DDR ECC Enable : %x\n", DdrParV1->BaseConfig.Bits.Ecc));
    DEBUG ((DEBUG_INFO, "Spd Force : %x\n", DdrParV1->BaseConfig.Bits.SpdForce));
    DEBUG ((DEBUG_INFO, "Dq Oe Timing mode 2 : %x\n", DdrParV1->BaseConfig.Bits.DqOeTiming2));
    DEBUG ((DEBUG_INFO, "Multi Rank Performance Enable : %x\n", DdrParV1->BaseConfig.Bits.MultiRankPerformance));
    DEBUG ((DEBUG_INFO, "Double Rank Stable Enable : %x\n", DdrParV1->BaseConfig.Bits.DoubleRankStable));
    DEBUG ((DEBUG_INFO, "2X Refresh Enable : %x\n", DdrParV1->BaseConfig.Bits.X2Refresh));
    DEBUG ((DEBUG_INFO, "Low Power Enable : %x\n", DdrParV1->BaseConfig.Bits.LowPower));
    DEBUG ((DEBUG_INFO, "DM Enable : %x\n", DdrParV1->BaseConfig.Bits.DmEnable));
    DEBUG ((DEBUG_INFO, "2T Preamble Plus Enable : %x\n", DdrParV1->BaseConfig.Bits.Preamble2TPlus));
    DEBUG ((DEBUG_INFO, "Pda Invert : %x\n", DdrParV1->BaseConfig.Bits.PdaInvert));
    DEBUG ((DEBUG_INFO, "Dq Oe Timing Mode 1 : %x\n", DdrParV1->BaseConfig.Bits.DqOeTiming1));
    DEBUG ((DEBUG_INFO, "One Two : %x\n", DdrParV1->BaseConfig.Bits.OneTwo));
    DEBUG ((DEBUG_INFO, "Performance Mode Enable : %x\n", DdrParV1->BaseConfig.Bits.Performance));
    DEBUG ((DEBUG_INFO, "2T Preamble Enable : %x\n", DdrParV1->BaseConfig.Bits.T2Preamble));
    DEBUG ((DEBUG_INFO, "Skip Scrub : %x\n", DdrParV1->BaseConfig.Bits.SkipScrub));
    DEBUG ((DEBUG_INFO, "Training Debug Controll :\n"));
    DEBUG ((DEBUG_INFO, "Training Delay.... : %x", DdrParV1->Debug.Bits.Delay));
    DEBUG ((DEBUG_INFO, "Training Result.... : %x", DdrParV1->Debug.Bits.Detailed));
    DEBUG ((DEBUG_INFO, "All Registers.... : %x", DdrParV1->Debug.Bits.Register));
    DEBUG ((DEBUG_INFO, "Error Information.... : %x", DdrParV1->Debug.Bits.Error));
    DEBUG ((DEBUG_INFO, "Training Recover : %x\n", DdrParV1->Recover));
    DEBUG ((DEBUG_INFO, "Training Parameter :\n"));
    DEBUG ((DEBUG_INFO, "Cpu Odt :\n", DdrParV1->Param.Bits.CpuOdt));
    DEBUG ((DEBUG_INFO, "Cpu Drv :\n", DdrParV1->Param.Bits.CpuDrv));
    DEBUG ((DEBUG_INFO, "Mr Drv :\n", DdrParV1->Param.Bits.MrDrv));
    DEBUG ((DEBUG_INFO, "Rtt Nom :\n", DdrParV1->Param.Bits.RttNom));
    DEBUG ((DEBUG_INFO, "Rtt Park :\n", DdrParV1->Param.Bits.RttPark));
    DEBUG ((DEBUG_INFO, "Rtt Wr :\n", DdrParV1->Param.Bits.RttWr));
    for (Index = 0; Index < 2; Index++) {
      DEBUG ((DEBUG_INFO, "Channel[%d] DDR Information :\n "));
      DEBUG ((DEBUG_INFO, " Dimm Type : %x\n", DdrParV1->ChannelInfo[Index].DimmType));
      DEBUG ((DEBUG_INFO, " Data Width : %x\n", DdrParV1->ChannelInfo[Index].DataWidth));
      DEBUG ((DEBUG_INFO, " Mirror Type : %x\n", DdrParV1->ChannelInfo[Index].MirrorType));
      DEBUG ((DEBUG_INFO, " Ecc Type : %x\n", DdrParV1->ChannelInfo[Index].EccType));
      DEBUG ((DEBUG_INFO, " Rank Num : %x\n", DdrParV1->ChannelInfo[Index].RankNum));
      DEBUG ((DEBUG_INFO, " Row Num : %x\n", DdrParV1->ChannelInfo[Index].RowNum));
      DEBUG ((DEBUG_INFO, " Column Num : %x\n", DdrParV1->ChannelInfo[Index].ColumnNum));
      DEBUG ((DEBUG_INFO, " Bank Group Num : %x\n", DdrParV1->ChannelInfo[Index].BankGroupNum));
      DEBUG ((DEBUG_INFO, " Bank Num : %x\n", DdrParV1->ChannelInfo[Index].BankNum));
      DEBUG ((DEBUG_INFO, " Module Manufacturer ID : %x\n", DdrParV1->ChannelInfo[Index].ModuleManId));
      DEBUG ((DEBUG_INFO, " tAAmin : %x\n", DdrParV1->ChannelInfo[Index].TAAmin));
      DEBUG ((DEBUG_INFO, " tRCDmin : %x\n", DdrParV1->ChannelInfo[Index].TRCDmin));
      DEBUG ((DEBUG_INFO, " tRPmin : %x\n", DdrParV1->ChannelInfo[Index].TRPmin));
      DEBUG ((DEBUG_INFO, " tRASmin : %x\n", DdrParV1->ChannelInfo[Index].TRASmin));
      DEBUG ((DEBUG_INFO, " tRCmin : %x\n", DdrParV1->ChannelInfo[Index].TRCmin));
      DEBUG ((DEBUG_INFO, " tFAWmin : %x\n", DdrParV1->ChannelInfo[Index].TFAWmin));
      DEBUG ((DEBUG_INFO, " tRRD_Smin : %x\n", DdrParV1->ChannelInfo[Index].TRRDSmin));
      DEBUG ((DEBUG_INFO, " tRRD_Lmin : %x\n", DdrParV1->ChannelInfo[Index].TRRDLmin));
      DEBUG ((DEBUG_INFO, " tCCD_Lmin : %x\n", DdrParV1->ChannelInfo[Index].TCCDLmin));
      DEBUG ((DEBUG_INFO, " tWR_min : %x\n", DdrParV1->ChannelInfo[Index].TWRmin));
      DEBUG ((DEBUG_INFO, " tWTR_Smin : %x\n", DdrParV1->ChannelInfo[Index].TWTRSmin));
      DEBUG ((DEBUG_INFO, " tWTR_Lmin : %x\n", DdrParV1->ChannelInfo[Index].TWTRLmin));
    }
    break;
  case PM_DDR_V2:
    DdrParV2 = (PARAMETER_DDR_CONFIG_V2 *) Buffer;
    PrintParameterHeader ((VOID *) &DdrParV2->Head);
    DEBUG ((DEBUG_INFO, "Channel Enable Bit Map : 0x%x\n", DdrParV2->BitMap));
    DEBUG ((DEBUG_INFO, "MCU Base config :\n"));
    DEBUG ((DEBUG_INFO, "Spd Force : %x\n", DdrParV2->BaseConfig.Bits.SpdForce));
    DEBUG ((DEBUG_INFO, "DDR ECC Enable : %x\n", DdrParV2->BaseConfig.Bits.EccEnable));
    DEBUG ((DEBUG_INFO, "DM Enable : %x\n", DdrParV2->BaseConfig.Bits.DmEnable));
    DEBUG ((DEBUG_INFO, "Performance Mode Enable : %x\n", DdrParV2->BaseConfig.Bits.Performance));
    DEBUG ((DEBUG_INFO, "2T Preamble Enable : %x\n", DdrParV2->BaseConfig.Bits.T2Preamble));
    DEBUG ((DEBUG_INFO, "One Two : %x\n", DdrParV2->BaseConfig.Bits.OneTwo));
    DEBUG ((DEBUG_INFO, "Skip Memory Clean : %x\n", DdrParV2->BaseConfig.Bits.SkipMemClean));
    DEBUG ((DEBUG_INFO, "Pda Invert : %x\n", DdrParV2->BaseConfig.Bits.PdaInvert));
    DEBUG ((DEBUG_INFO, "Dq Oe Timing mode : %x\n", DdrParV2->BaseConfig.Bits.DqOeTiming));
    DEBUG ((DEBUG_INFO, "Multi Rank Performance Enable : %x\n", DdrParV2->BaseConfig.Bits.MultiRankHigh));
    DEBUG ((DEBUG_INFO, "2X Refresh Enable : %x\n", DdrParV2->BaseConfig.Bits.X2Fresh));
    DEBUG ((DEBUG_INFO, "Auto Low Power Enable : %x\n", DdrParV2->BaseConfig.Bits.AutoLowPower));
    DEBUG ((DEBUG_INFO, "Half Bit Mode Width : %x\n", DdrParV2->BaseConfig.Bits.HalfBitWidth));
    DEBUG ((DEBUG_INFO, "DBI Enable : %x\n", DdrParV2->BaseConfig.Bits.Dbi));
    DEBUG ((DEBUG_INFO, "Training Debug Controll :\n"));
    DEBUG ((DEBUG_INFO, "Training Delay.... : %x", DdrParV2->Debug.Bits.Delay));
    DEBUG ((DEBUG_INFO, "Training Result.... : %x", DdrParV2->Debug.Bits.Detailed));
    DEBUG ((DEBUG_INFO, "All Registers.... : %x", DdrParV2->Debug.Bits.Register));
    DEBUG ((DEBUG_INFO, "Error Information.... : %x", DdrParV2->Debug.Bits.Error));
    DEBUG ((DEBUG_INFO, "Training Recover : %x\n", DdrParV2->Recover));
    DEBUG ((DEBUG_INFO, "Specify Dram Type : %x\n", DdrParV2->SpecifyDramType));
    for (Index = 0; Index < 6; Index++) {
      DEBUG ((DEBUG_INFO, "Training Param[%d] : %x\n", Index, DdrParV2->TrainParam[Index]));
    }
    DEBUG ((DEBUG_INFO, "DDR Type Swap Only for LPDDR4 :\n"));
    for (Index = 0; Index < 8; Index++) {
      DEBUG ((DEBUG_INFO, "Data Swap[%d] - %x\n", Index, (DdrParV2->DataSwap.Uint32 >> (Index * 4)) & 0xF));
    }
    for (Index = 0; Index < 8; Index++) {
      DEBUG ((DEBUG_INFO, "DDR Slice[%d] DQ Swizzle - %x\n", Index, DdrParV2->DqSwizzle[Index]));
    }
    DEBUG ((DEBUG_INFO, "DDR Channel Information :\n"));
    DEBUG ((DEBUG_INFO, " Dimm Type : %x\n", DdrParV2->ChannelInfo.DimmType));
    DEBUG ((DEBUG_INFO, " Data Width : %x\n", DdrParV2->ChannelInfo.DataWidth));
    DEBUG ((DEBUG_INFO, " Mirror Type : %x\n", DdrParV2->ChannelInfo.MirrorType));
    DEBUG ((DEBUG_INFO, " Ecc Type : %x\n", DdrParV2->ChannelInfo.EccType));
    DEBUG ((DEBUG_INFO, " dram Type : %x\n", DdrParV2->ChannelInfo.DramType));
    DEBUG ((DEBUG_INFO, " Rank Num : %x\n", DdrParV2->ChannelInfo.RankNum));
    DEBUG ((DEBUG_INFO, " Row Num : %x\n", DdrParV2->ChannelInfo.RowNum));
    DEBUG ((DEBUG_INFO, " Column Num : %x\n", DdrParV2->ChannelInfo.ColumnNum));
    DEBUG ((DEBUG_INFO, " Bank Group Num : %x\n", DdrParV2->ChannelInfo.BankGroupNum));
    DEBUG ((DEBUG_INFO, " Bank Num : %x\n", DdrParV2->ChannelInfo.BankNum));
    DEBUG ((DEBUG_INFO, " Module Manufacturer ID : %x\n", DdrParV2->ChannelInfo.ModuleManId));
    DEBUG ((DEBUG_INFO, " tAAmin : %x\n", DdrParV2->ChannelInfo.TAAmin));
    DEBUG ((DEBUG_INFO, " tRCDmin : %x\n", DdrParV2->ChannelInfo.TRCDmin));
    DEBUG ((DEBUG_INFO, " tRPmin : %x\n", DdrParV2->ChannelInfo.TRPmin));
    DEBUG ((DEBUG_INFO, " tRASmin : %x\n", DdrParV2->ChannelInfo.TRASmin));
    DEBUG ((DEBUG_INFO, " tRCmin : %x\n", DdrParV2->ChannelInfo.TRCmin));
    DEBUG ((DEBUG_INFO, " tFAWmin : %x\n", DdrParV2->ChannelInfo.TFAWmin));
    DEBUG ((DEBUG_INFO, " tRRD_Smin : %x\n", DdrParV2->ChannelInfo.TRRDSmin));
    DEBUG ((DEBUG_INFO, " tRRD_Lmin : %x\n", DdrParV2->ChannelInfo.TRRDLmin));
    DEBUG ((DEBUG_INFO, " tCCD_Lmin : %x\n", DdrParV2->ChannelInfo.TCCDLmin));
    DEBUG ((DEBUG_INFO, " tWR_min : %x\n", DdrParV2->ChannelInfo.TWRmin));
    DEBUG ((DEBUG_INFO, " tWTR_Smin : %x\n", DdrParV2->ChannelInfo.TWTRSmin));
    DEBUG ((DEBUG_INFO, " tWTR_Lmin : %x\n", DdrParV2->ChannelInfo.TWTRLmin));
    DEBUG ((DEBUG_INFO, " tRFC1_min : %x\n", DdrParV2->ChannelInfo.TWTRLmin));
    DEBUG ((DEBUG_INFO, " TRFC2_min : %x\n", DdrParV2->ChannelInfo.TRFC2min));
    DEBUG ((DEBUG_INFO, " TRFC4_RFCsbmin : %x\n", DdrParV2->ChannelInfo.TRFC4RFCsbmin));
    break;
  case PM_DDR_V3:
    DdrParV3 = (PARAMETER_DDR_CONFIG_V3 *) Buffer;
    PrintParameterHeader ((VOID *) &DdrParV3->Head);
    DEBUG ((DEBUG_INFO, "Channel Enable Bit Map : 0x%llx\n", DdrParV3->ChEnableMap));
    DEBUG ((DEBUG_INFO, "MCU Base Config :\n"));
    DEBUG ((DEBUG_INFO, "Spd Force : %x\n", DdrParV3->McuConfig.Bits.SpdForce));
    DEBUG ((DEBUG_INFO, "Ecc Enable : %x\n", DdrParV3->McuConfig.Bits.EccEnable));
    DEBUG ((DEBUG_INFO, "DM Enable : %x\n", DdrParV3->McuConfig.Bits.DMEnable));
    DEBUG ((DEBUG_INFO, "Performance Enable : %x\n", DdrParV3->McuConfig.Bits.Performance));
    DEBUG ((DEBUG_INFO, "2T Preamble Enable : %x\n", DdrParV3->McuConfig.Bits.Preamble2T));
    DEBUG ((DEBUG_INFO, "One Two : %x\n", DdrParV3->McuConfig.Bits.OneTwo));
    DEBUG ((DEBUG_INFO, "Skip Memory clean : %x\n", DdrParV3->McuConfig.Bits.SkipMemClean));
    DEBUG ((DEBUG_INFO, "Pda Invert : %x\n", DdrParV3->McuConfig.Bits.PdaInvert));
    DEBUG ((DEBUG_INFO, "DQ OE Timing : %x\n", DdrParV3->McuConfig.Bits.DqoeTiming));
    DEBUG ((DEBUG_INFO, "Multi Rank Performance : %x\n", DdrParV3->McuConfig.Bits.MultiRankPer));
    DEBUG ((DEBUG_INFO, "Auto Low Power Enable : %x\n", DdrParV3->McuConfig.Bits.AutoLowPower));
    DEBUG ((DEBUG_INFO, "Half Bit Width : %x\n", DdrParV3->McuConfig.Bits.HalfBitWidth));
    DEBUG ((DEBUG_INFO, "DBI Mode : %x\n", DdrParV3->McuConfig.Bits.Dbi));
    DEBUG ((DEBUG_INFO, "Refresh Mode : %x\n", DdrParV3->McuConfig.Bits.RefreshMode));
    DEBUG ((DEBUG_INFO, "Temp Refresh : %x\n", DdrParV3->McuConfig.Bits.TempRefresh));
    DEBUG ((DEBUG_INFO, "CRC Enable : %x\n", DdrParV3->McuConfig.Bits.Crc));
    DEBUG ((DEBUG_INFO, "CA Parity : %x\n", DdrParV3->McuConfig.Bits.CaParity));
    DEBUG ((DEBUG_INFO, "DDR5 ECS : %x\n", DdrParV3->McuConfig.Bits.Ddr5Ecs));
    DEBUG ((DEBUG_INFO, "Training Debug Controll :\n"));
    DEBUG ((DEBUG_INFO, "Training Delay.... : %x", DdrParV3->DebugInfo.Bits.Delay));
    DEBUG ((DEBUG_INFO, "Training Result.... : %x", DdrParV3->DebugInfo.Bits.Detailed));
    DEBUG ((DEBUG_INFO, "All Registers.... : %x", DdrParV3->DebugInfo.Bits.Register));
    DEBUG ((DEBUG_INFO, "Error Information.... : %x", DdrParV3->DebugInfo.Bits.Error));
    DEBUG ((DEBUG_INFO, "Training Recover : %x\n", DdrParV3->TrainingRecover));
    DEBUG ((DEBUG_INFO, "Specify Dram Type : %x\n", DdrParV3->DramType));
    for (Index = 0; Index < 6; Index++) {
      DEBUG ((DEBUG_INFO, "Training Param[%d] : %x\n", Index, DdrParV3->TrainingPar[Index]));
    }
    DEBUG ((DEBUG_INFO, "DDR Type Swap Only for LPDDR4 :\n"));
    for (Index = 0; Index < 8; Index++) {
      DEBUG ((DEBUG_INFO, "Data Swap[%d] - %x\n", Index, (DdrParV3->Swap.Uint32 >> (Index * 4)) & 0xF));
    }
    for (Index = 0; Index < 8; Index++) {
      DEBUG ((DEBUG_INFO, "DDR Slice[%d] DQ Swizzle - %x\n", Index, DdrParV3->SliceDqSwizzle[Index]));
    }
    DEBUG ((DEBUG_INFO, "DDR Channel Information :\n"));
    DEBUG ((DEBUG_INFO, " Dimm Type : %x\n", DdrParV3->ChannelInfo.DimmType));
    DEBUG ((DEBUG_INFO, " Data Width : %x\n", DdrParV3->ChannelInfo.DataWidth));
    DEBUG ((DEBUG_INFO, " Mirror Type : %x\n", DdrParV3->ChannelInfo.MirrorType));
    DEBUG ((DEBUG_INFO, " Ecc Type : %x\n", DdrParV3->ChannelInfo.EccType));
    DEBUG ((DEBUG_INFO, " dram Type : %x\n", DdrParV3->ChannelInfo.DramType));
    DEBUG ((DEBUG_INFO, " Rank Num : %x\n", DdrParV3->ChannelInfo.RankNum));
    DEBUG ((DEBUG_INFO, " Row Num : %x\n", DdrParV3->ChannelInfo.RowNum));
    DEBUG ((DEBUG_INFO, " Column Num : %x\n", DdrParV3->ChannelInfo.ColumnNum));
    DEBUG ((DEBUG_INFO, " Bank Group Num : %x\n", DdrParV3->ChannelInfo.BankGroupNum));
    DEBUG ((DEBUG_INFO, " Bank Num : %x\n", DdrParV3->ChannelInfo.BankNum));
    DEBUG ((DEBUG_INFO, " Module Manufacturer ID : %x\n", DdrParV3->ChannelInfo.ModuleManId));
    DEBUG ((DEBUG_INFO, " tAAmin : %x\n", DdrParV3->ChannelInfo.TAAmin));
    DEBUG ((DEBUG_INFO, " tRCDmin : %x\n", DdrParV3->ChannelInfo.TRCDmin));
    DEBUG ((DEBUG_INFO, " tRPmin : %x\n", DdrParV3->ChannelInfo.TRPmin));
    DEBUG ((DEBUG_INFO, " tRASmin : %x\n", DdrParV3->ChannelInfo.TRASmin));
    DEBUG ((DEBUG_INFO, " tRCmin : %x\n", DdrParV3->ChannelInfo.TRCmin));
    DEBUG ((DEBUG_INFO, " tFAWmin : %x\n", DdrParV3->ChannelInfo.TFAWmin));
    DEBUG ((DEBUG_INFO, " tRRD_Smin : %x\n", DdrParV3->ChannelInfo.TRRDSmin));
    DEBUG ((DEBUG_INFO, " tRRD_Lmin : %x\n", DdrParV3->ChannelInfo.TRRDLmin));
    DEBUG ((DEBUG_INFO, " tCCD_Lmin : %x\n", DdrParV3->ChannelInfo.TCCDLmin));
    DEBUG ((DEBUG_INFO, " tWR_min : %x\n", DdrParV3->ChannelInfo.TWRmin));
    DEBUG ((DEBUG_INFO, " tWTR_Smin : %x\n", DdrParV3->ChannelInfo.TWTRSmin));
    DEBUG ((DEBUG_INFO, " tWTR_Lmin : %x\n", DdrParV3->ChannelInfo.TWTRLmin));
    DEBUG ((DEBUG_INFO, " tRFC1_min : %x\n", DdrParV3->ChannelInfo.TWTRLmin));
    DEBUG ((DEBUG_INFO, " TRFC2_min : %x\n", DdrParV3->ChannelInfo.TRFC2min));
    DEBUG ((DEBUG_INFO, " TRFC4_RFCsbmin : %x\n", DdrParV3->ChannelInfo.TRFC4RFCsbmin));
    DEBUG ((DEBUG_INFO, "RAS Config :\n"));
    DEBUG ((DEBUG_INFO, " Enable : %x\n", DdrParV3->RasConfig.RasEnable.Bits.Enable));
    DEBUG ((DEBUG_INFO, " Value : %x\n", DdrParV3->RasConfig.Value));
    break;
  default:
    break;
  }
}

/**
  Print board parameter information.

  @param[in]  Id      Parameter ID.
                      PM_BOARD_V2 for Ps2364.

  @param[in]  Buffer  Buffer to print.

**/
VOID
PrintBoardParameter (
  IN UINT32  Id,
  IN VOID    *Buffer
  )
{
  PARAMETER_BOARD_CONFIG_V2  *BoardParV2;
  UINT32                     Index;

  DEBUG ((DEBUG_INFO, "BOARD Parameter :\n"));
  switch (Id) {
  case PM_BOARD_V2:
    BoardParV2 = (PARAMETER_BOARD_CONFIG_V2 *) Buffer;
    PrintParameterHeader ((VOID *) &BoardParV2->Head);
    DEBUG ((DEBUG_INFO, "Bmc Enable : %x\n", BoardParV2->BmcEnable));
    for (Index = 0; Index < 8; Index++) {
      //DEBUG ((DEBUG_INFO, "POWER IC [%d] CONFIG:\n", Index));
      //DEBUG ((DEBUG_INFO, "Enable : %x\n", BoardParV2->PowerIc[Index].Enable));
      //DEBUG ((DEBUG_INFO, "SlaveAddr : 0x%02x\n", BoardParV2->PowerIc[Index].SlaveAddr));
      //DEBUG ((DEBUG_INFO, "Mode : 0x%08x\n", BoardParV2->PowerIc[Index].Mode));
      //DEBUG ((DEBUG_INFO, "Vlsb : 0x%08x\n", BoardParV2->PowerIc[Index].Vlsb));
      //DEBUG ((DEBUG_INFO, "Ilsb : 0x%08x\n", BoardParV2->PowerIc[Index].Ilsb));
      //DEBUG ((DEBUG_INFO, "Plsb : 0x%08x\n", BoardParV2->PowerIc[Index].Plsb));
    }
    break;
  default:
    break;
  }
}
